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・ Transmembrane domain
・ Transmembrane domain of ABC transporters
・ Transmembrane protein
・ Transmembrane protein 134
・ Transmembrane protein 151a
・ Transmembrane protein 151b
・ Transmembrane Protein 175
・ Transmembrane Protein 205
・ Transmembrane protein 222
・ Transmembrane protein 251
・ Transmembrane protein 53
・ Transmeridian Air Cargo
・ TransMeridian Airlines
・ Transmeta
・ Transmeta Crusoe
Transmeta Efficeon
・ Transmetal
・ Transmetal (band)
・ Transmetal 2
・ Transmetalation
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Transmeta Efficeon : ウィキペディア英語版
Transmeta Efficeon

The Efficeon processor is Transmeta's second-generation 256-bit VLIW design which employs a software engine to convert code written for x86 processors to the native instruction set of the chip (Code Morphing Software, aka CMS). Like its predecessor, the Transmeta Crusoe (a 128-bit VLIW architecture), Efficeon stresses computational efficiency, low power consumption, and a low thermal footprint.
Efficeon most closely mirrors the feature set of Intel Pentium 4 processors, although, like AMD Opteron processors, it supports a fully integrated memory controller, a HyperTransport IO bus, and the NX bit, or no-execute x86 extension to PAE mode. NX bit support is available starting with CMS version 6.0.4.
Efficeon's computational performance relative to mobile CPUs like the Intel Pentium M is thought to be lower, although little appears to be published about the relative performance of these competing processors.
Efficeon came in two package types: a 783- and a 592-contact ball grid array. Its power consumption is moderate (with some consuming as little as 3 watts at 1 GHz and 7 watts at 1.5 GHz), so it can be passively cooled.
Two generations of this chip were produced. The first generation (TM8600) was manufactured using a TSMC 0.13 micrometre process and produced at speeds up to 1.2 GHz. The second generation (TM8800 and TM8820) was manufactured using a Fujitsu 90 nm process and produced at speeds ranging from 1 GHz to 1.7 GHz.
Internally, the Efficeon has two arithmetic logic units, two load/store/add units, two execute units, two floating-point/MMX/SSE/SSE2 units, one branch prediction unit, one alias unit, and one control unit. The VLIW core can execute a 256-bit VLIW instruction per cycle, which is called a molecule and has room to store eight 32-bit instructions (called atoms) per cycle.
The Efficeon has a 128 KB L1 instruction cache, a 64 KB L1 data cache and a 1 MB L2 cache. All caches are on die.
Additionally the Efficeon CMS (code morphing software) reserves a small portion of main memory (typically 32 MB) for its translation cache of dynamically translated x86 instructions.
==Products==

* Sharp Actius MM20
* Sharp Actius MP30
* Sharp Mebius Muramasa PC-MM2
* Sharp Mebius Muramasa PC-CV50F
* Sharp MP70G
* Orion Multisystem Cluster Workstation
* the first generation Microsoft FlexGo Computer〔(Microsoft brings Vista to developing world PCs )〕
* Elitegroup A532

抄文引用元・出典: フリー百科事典『 ウィキペディア(Wikipedia)
ウィキペディアで「Transmeta Efficeon」の詳細全文を読む



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